Data processing method and apparatus including iterative multiplier
US5557563A · kind A · utility
8Cited by
2References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Aug 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5324
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An iterative multiplier having a multiplier core generating partial results upon each iteration. When an early terminate of a multiply instruction occurs, at least one of the partial results is passed to a general purpose barrel shifter for bit realignment dependent upon the number of iterations performed before the early terminate occurred. The bit realigned partial results are then passed to an arithmetic logic unit where they are added to yield the final result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.