Phase lock loop circuit using a sample and hold switch circuit
US5557648A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Feb 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase lock loop circuit that can be formed into a full monolithic integrated circuit without an external component part, and that can maintain the phase locked state even for a consecutive identical bit state of input data including more than several tens of consecutive identical bits. The input data applied to a data input terminal is doubled in frequency by a doubler. A phase difference between the output of the doubler and that of a VCO is detected by a phase comparator, and is supplied to a low-pass filter through a sample and hold switch circuit. The low-pass filter produces a DC output corresponding to the phase difference, and supplies it to the frequency control terminal of the VCO. The output frequency of the VCO is controlled so that the phase difference becomes zero. The sample and hold switch circuit is maintained at the off state (holding mode) during the consecutive identical bit state to hold the output of the low-pass filter, so that the VCO continues that frequency at the beginning of the consecutive identical bit state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.