Circuit configuration for dividing a clock signal

US5557649A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bruno Scheckel · Ebersberg, DE
• Stefan Heinen · Krefeld, DE
• Jean Wilwert · Hersbruck, DE
• Helmut Herrmann · Hersbruck, DE

Key dates

• Filing date: May 17, 1995
• Grant date: Sep 17, 1996
• Expiry date: May 17, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K23/667
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and a clock input. The output of the second flip-flop is coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops are acted upon by a clock signal. A first AND gate is connected upstream of the first flip-flop and has a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop. A second AND gate is connected between the first and second flip-flops and has an output connected to the data input of the second flip-flop, a first input receiving an inverted signal from the output of the first flip-flop, and a second input being acted upon by the inverted signal from the output of the third flip-flop.