Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors
US5557744A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1993 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Jul 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit. An interruption processing unit receives an interrupt request from the reception unit, supervises the vacant/full state of the transfer queue unit, i.e. monitors whether the transfer queue unit has an area available for storing a transfe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.