Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses
US5557758A · kind A · utility
36Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Nov 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.