Flexible deterministic state machine
US5557782A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Jul 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system has a memory and has a processor coupled to the memory, the processor having an access control arrangement for delaying completion of a memory access until the occurrence of a control signal. A deterministic circuit coupled to the-processor and the memory has a register arrangement containing control information loaded by the processor, the deterministic circuit having a signal generation arrangement for generating the control signal. The signal generating arrangement includes a selective delay arrangement which can selectively delay generation of the control signal during an access to the memory by a time interval having a duration which is a function of the control information in the register arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.