Scheduling method for automatically developing hardware patterns for integrated circuits
US5557797A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1995 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Dec 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheduling method for scheduling a program comprises the steps of: extracting a plurality of traces from a given program such that each of the traces contains a plurality of program blocks executed sequentially, each of the plurality of program blocks containing one or more operators to be executed by arithmetic units of a computer and being separated from another program block in the trace by a branching step that causes a branching to or from a program block outside of the trace; extracting, in each of the plurality of traces, a critical path of the operation conducted by the operators in the trace, the critical path being formed of a plurality of reference operators, the rest of the operators forming movable operators that are conducted concurrently with one or more of the reference operators; and scheduling, in each of the traces, the processing steps of the movable operators such that the maximum of the number of the movable operators conducted concurrently to a reference operator in a given trace, is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.