Off-chip impedance matching utilizing a dielectric element and high density interconnect technology
US5559363A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-frequency, high-power, semiconductor device chip is impedance matched to an off-chip impedance by a matching network including a dielectric element located on a substrate ground plane portion adjacent to the device to be matched. A thin film dielectric layer is formed over the dielectric element, the semiconductor device and the surrounding substrate. A patterned metal matching circuit is disposed over the dielectric layer and is in electrical contact with an electrode of the high-frequency, high-power, semiconductor device. An impedance matching network is formed by the patterned metal circuit, the dielectric element, the dielectric layer and the underlying grounded substrate. The matching characteristics of the network can be tailored by selecting suitable dielectric materials for the dielectric element and by altering design of the patterned metal circuit. This fabrication of a high-density-interconnect (HDI) structure provides a method for altering the patterned metal circuit by laser lithography, such that a matching circuit can be uniquely tailored to the individual circuit during manufacture, and eliminating the need to mechanically tune the circuit or stock various v…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.