Circuit technique that sets transconductance
US5559470A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Feb 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/0466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52dB) of total harmonic distortion when processing 2Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36Mbps, and is built in a 1.5 .mu./4GHz BiCMOS technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.