Pulse generator having controlled delay to control duty cycle
US5559477A · kind A · utility
3Cited by
11References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Sep 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.