Method and apparatus for parallel pixel hardware cursor
US5559532A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1994 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Nov 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display system displays a cursor on a monitor using parallel pixels of video data. A hardware cursor processor receives a sequence of clock signals, cursor data, parallel video data arranged in P logical pixels per clock signal, and cursor position data. The hardware cursor processor provides composite video data representative of the cursor data and the video data to a memory. The composite video data is arranged in P logical pixels per clock signal. The hardware cursor processor arranges the cursor data within the P logical pixels per clock signal in response to the cursor position data. The cursor position data includes a position signal HPOS indicative of the horizontal position of the cursor on the screen and includes a preset signal HPRE indicative of the horizontal offset of the cursor. The cursor data is arranged within the P logical pixels of the composite video data to begin at the logical pixel equal to [(HPOS-HPRE) modulus P]. A memory has an input coupled to the output of the hardware cursor processor and has an output for providing a digital video signal indicative of the video data and the cursor data. A digital-to-analog converter has an input coupled to the outpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.