Non-conforming PCI bus master timing compensation circuit
US5559968A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Mar 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for preventing a non-conforming PCI bus master from performing cycles where the address driven is not provided soon enough for receiving circuitry to latch the address. The circuit modifies the bus grant signal to force the non-conforming PCI bus master to temporarily release the bus instead of performing a second data transfer cycle within the same bus access so that a conforming cycle is subsequently performed when the bus is reacquired by the non-conforming PCI bus master. The circuit forces the non-conforming PCI bus master off the bus even though the non-conforming PCI bus requests the bus and an arbiter has granted the bus to the non-conforming PCI bus master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.