Apparatus and method for protecting data in a memory address range
US5559992A · kind A · utility
19Cited by
9References
64Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1993 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Jan 11, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data protection apparatus has chip select logic, a protection circuit and one or more memory devices. The chip select logic is designed so that when protected memory is addressed, more than one selection signal is generated. In this way, a protected memory area may encompass all, or a portion, of one or more memory devices. The additional selection signal is processed by a protection circuit which will interrupt the processor if protected memory is addressed during a write cycle in the absence of a request signal which the processor is programmed to generate just prior to its writing to a protected memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.