Method and apparatus for handling interrupts in a multiprocessor computer system
US5560019A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 1996 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Jan 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt steering control mechanism includes an interrupt target register storing a code identifying a particular interrupt target processor to receive undirected interrupts within a multiple processor computer system. The computer operating system assigns a particular processor to be a current interrupt target by writing the identifying processor code in to the interrupt target register. A system interrupt pending register permits any processor to ascertain whether an interrupt source has requested service. Each interrupt service request is assigned an interrupt priority determining when the particular processor will service the interrupt in relation to other interrupts pending for that processor. An interrupt target mask register permits the current interrupt target processor to delay service of the interrupt request until some later time, and any processor may assert ownership of the current interrupt target. Appropriate bits within a processor interrupt register for each processor indicates whether soft or hard directed interrupts at any priority level are pending for that processor. The processor identified to be the current interrupt target also receives pending hard undi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.