Software scheduled superscalar computer architecture
US5560028A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Apr 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.