Self-diagnostic device for semiconductor memories
US5561671A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1995 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Oct 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-diagnostic device for checking the performance of memory matrix in semiconductor devices is presented. The device is applicable particularly to those IC testers having high bit and high capacity memories. The device is capable of performing march and checker tasks simultaneously. The program data contained in a CPU 1 are written into the memory matrix 5 by way of the data generation circuit 2 and the address generation circuit 3. The test data are entered into a comparator 4 at the timing governed by the clock generation circuit 6, and are compared with the expected data from the data generation circuit 2. When there is a non-coincidence, a defect signal is generated from a flip-flop (FF) circuit 9. In the present device, the conventional division circuits are replaced by two FF circuits 8, 9, and two EOR-gates 11, 12 and associated components to provide simplicity in circuit configuration and efficient operation while retaining the advantages offered by the conventional march- and checker-modes. The FF circuit 8 provides a set/reset-signal in response to a clock signal from the clock generation circuit 6. The EOR-gate 12 operates so as to generate an inverted signal of the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.