Malicious fault list generation method
US5561762A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for selecting and responding to a malicious fault in a reconfigurable electronic apparatus that can perform multiple tasks, and that has fault processing for counteracting a class of faults which can generally cause the apparatus to fail during the execution of a preselected task if the fault processor is unavailable and to which class the malicious fault can belong. The reconfigurable electronic apparatus can be a fault processing system, which can be an interlocking control circuit, or a combinational circuit. The method includes constructing an information flow representation of at least a portion of the apparatus executing the preselected task of interest; applying a preselected fault representation to the information flow representation and producing multiple input error conditions corresponding to at least one preselected output condition, the preselected fault representation including recursive reverse implication and, where reconvergent fanout occurs, a forward consistency check; selecting from the aforementioned multiple input error conditions at least one fault condition corresponding to the class of faults; injecting the at least one fault condition into the inf…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.