Programmable, multi-purpose virtual pin multiplier
US5561773A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and circuitry is provided by which certain selected embedded pins of an integrated circuit gate array may be provided with dual functions, that is to say, they may act either as receivers of an externally sourced input signal or as transmitters of an internally generated output signal. Each selected input/output pin is controlled by an associated flip-flop residing in a chain of flip-flops so that an associated flip-flop will determine the condition of two buffer-drivers attached to each input/output pin. While the first buffer-driver is tri-stated (disabled), then the embedded pin operates as an input receiving function. When the first buffer-driver is enabled, the embedded I/O pin operates as the conveyer of an output signal from the internal output logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.