Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses
US5561784A · kind A · utility
71Cited by
79References
10Claims
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Key dates
| Filing date | Jun 29, 1994 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Jun 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.