Method of making a three-dimensional integrated circuit
US5563084A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Sep 22, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a three dimensionally integrated circuit by connecting first and second substrates (1;7) provided with devices in at least one layer in at least one surface in each of said substrates. An auxiliary substrate is connected to the one surface of one of said substrates which is then reduced in thickness from its opposite surface. The auxiliary layer with the devices thereon is then separated into individual chips which after having been found to be functioning are aligned and mounted in a side-by-side arrangement on said one surface of said first substrate. Electrical connection are formed between the devices of the mounted chips and the devices in the first substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.