Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes
US5563093A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | May 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides the method of manufacturing a dual-gate CMOS device which has high transconductance and improved breakdown voltage, in which depletion in the interface between a gate oxide and a gate electrode is prevented without the increase of the steps of process. A gate oxide film (5) formed on a semiconductor substrate (1) is washed with an aqueous solution, or exposed to a gas atomosphere containing hydrogen, and an amorphous silicon film (3) is formed on the whole surface of the gate oxide film (5). The amorphous silicon film (3) is then crystallized. Alternatively, after a silicon oxide film (53) or a silicon nitrided film is formed on the amorphous silicon film (3), the amorhpous silicon film (3) is crystallized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.