Method for fabricating semiconductor device
US5563097A · kind A · utility
Inventor
Key dates
| Filing date | Apr 17, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Apr 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for burying contact holes having different depths at the same time using selective tungsten deposition at the time of fabricating a semiconductor device. The method for fabricating a semiconductor device may include the steps of: forming a first insulation layer on a semiconductor substrate having first conduction lines formed thereon; forming a first contact hole by carrying out a selective etching of a designated part of the first insulation layer; forming a conduction layer over the first insulation layer including the first contact hole for forming a second conduction line; forming a TiN layer on the conduction layer; patterning the TiN layer and the conduction layer with a second conduction line pattern; planarizing the surface of the substrate by forming a second insulation layer on the second conduction line and the first insulation layer; forming second contact holes exposing each of the surfaces of the first conduction line and the second conduction line by carrying out a selective etching of designated parts of the second insulation layer and the first insulation layer; and fully and simultaneously burying each of the second contact holes by carrying out a select…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.