Method of sealing integrated circuits
US5563102A · kind A · utility
73Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to integrated circuits which are protected from the environment. Such circuits are sealed by applying a diffusion barrier metal layer to the bond pads and two passivation layers to the remainder of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.