Low leakage ESD network for protecting semiconductor devices and method of construction
US5563757A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/52
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low leakage ESD network (24) is provided for protecting a semiconductor device (22). The ESD network (24) comprises an ESD circuit (28) and a bias circuit (30). The ESD circuit (28) is connected to an input of the semiconductor device (22). The ESD circuit (28) is operable to protect the input of the semiconductor device (22) against electro-static discharge. The bias circuit (30) is connected to the input of the semiconductor device (22) and to the ESD circuit (28). The bias circuit (30) is operable to actively bias the ESD circuit (28) such that a voltage difference across each current leakage path in the ESD circuit (28) is held substantially equal to zero volts during normal operation of the semiconductor device (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.