Semiconductor memory device with data bus having plurality of I/O pins and with circuitry having latching and multiplexing function
US5563830A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Sep 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device disclosed includes a data bus, an I/O terminal, a distributing circuit, a multiplexer circuit, and a latching circuit. The data bus includes a plurality of I/O pins. The distributing circuit divides the data bus into a first data bus and a second data bus constituted by data bus signal lines, and controls a state of connections of the data bus signal lines such that the state is either a one-to-one connection state or a one-to-many connection state with respect to predetermined I/O pins. The multiplexer circuit divides the data bus between the distributing circuit and the memory cell array into the second data bus and a third data bus constituted by data bus signal lines, and controls a state of connections of the data bus signal lines such that the state is either a one-to-one connection state or a many-to-one connection state. The latching circuit latches signals outputted from the second data bus and inputs signals as control signals into the multiplexer circuit. The testing operations respectively for a plurality of I/O pins can be carried out without being limited by the number of drivers/comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.