Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions
US5564042A · kind A · utility
20Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1994 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Feb 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus. A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.