Mapping of gate arrays
US5565758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Oct 15, 1996 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.