Processor core which provides a linear extension of an addressable memory space
US5566308A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 1994 |
| Grant date | Oct 15, 1996 |
| Priority date | — |
| Expiry date | May 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/321
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.