Method and apparatus for adaptive memory access
US5566325A · kind A · utility
152Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1994 |
| Grant date | Oct 15, 1996 |
| Priority date | — |
| Expiry date | Jun 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.