Configurable XNOR/XOR element
US5568067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Jun 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.