Method and system for the design verification of logic units and use in different environments

US5568407A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jurgen Hass · Langen (Hessen), DE
• Rolf Hilgendorf · Eppelheim, DE
• Siegfried Neuber · Sindelfingen, DE
• Thomas Schlipf · Holzgerlingen, DE
• Hartmut Ulland · Stuttgart, DE

Key dates

• Filing date: Jun 6, 1995
• Grant date: Oct 22, 1996
• Expiry date: Jun 6, 2015

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/33
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.