Rounding-off method and apparatus of floating point arithmetic apparatus for addition/subtraction
US5568412A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1994 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Nov 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for arithmetic addition/subtraction of first and second floating point operands, each having a fraction portion and an exponent, includes an alignment circuit, an addition/subtraction-and-rounding-off circuit, and a normalization circuit. The alignment circuit aligns the fraction portions of the first and second operands based on a difference of their exponents obtained by comparing the respective exponents of the first and second operands. The addition/subtraction-and-rounding-off circuit performs at least two addition/subtraction operations between the aligned fraction portions of the first and second operands, and selectively outputs a result value of one of the addition/subtraction operations as a rounded-off result value in response to a rounding-off control signal so that the rounded-off result value is a rounded-off value of addition/subtraction of the fraction portions of the first and second operands. The normalization circuit normalizes the rounded-off result value to output a final result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.