Low power data latch with overdriven clock signals
US5568429A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Jul 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data latch with reduced data signal leakage includes a latch circuit and a clock buffer circuit which provides a differential clock signal to the input transmission gate of the latch circuit. The clock buffer circuit is biased between upper and lower supply voltage potentials which are higher and lower, respectively, than those between which the latch circuit is biased. This causes the differential clock signal to be overdriven with respect to the incoming data signal which is latched by the latch circuit. As a result, the input transmission gate of the latch circuit is reverse-biased during the inactive state of the differential clock signal, thereby isolating the storage node within the latch circuit and preventing signal leakage therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.