Self timed address locking and data latching circuit
US5568430A · kind A · utility
16Cited by
2References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides an address locking and data latching timing control circuit for use in DRAMs using Extended Data Out (EDO) mode. The Extended Data Out (EDO) mode reduces the page mode cycle time with the same data period. This can result in loss of data if the data is not fully established and latched before the next column address arrives. The address locking and data latching timing control circuit of this invention locks the address input buffer and latches the data output buffer until the data is fully established and latched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.