RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory
US5568442A · kind A · utility
13Cited by
16References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Jun 16, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RISC processor utilizes a segmented cache to reduce word line loading to reduce power consumption and increase speed. Address bit are predecoded to activate a selected segment. Groups of instructions are accessed from the cache in parallel and stored in register. The stored instructions are fetched from the register during sequential instruction execution to reduce the number of cache accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.