Circuit and method of JTAG testing multichip modules
US5568492A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1994 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Jun 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A multichip module (10) having one or more IC die (12-18) supports JTAG testing with a plurality of registers (20-26) within each IC die. JTAG testing requires a one cycle delay bypass mode where registers within an IC not under test are bypassed. To support bypass mode when JTAG testing the multichip module on a printed circuit board, a bypass circuit around the multichip module provides the one cycle delay. The bypass circuit monitors the test data signals to the multichip module and enters bypass mode upon detecting a predetermined sequence of logic states during the instruction sequence. Otherwise, the test data signal passes through a plurality of registers within each IC die. The detection may be performed by counting logic states or otherwise monitoring in the instruction sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.