Phase lock indicator circuit for a high frequency recovery loop
US5568521A · kind A · utility
17Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1993 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Sep 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2273
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.