Self timed interface
US5568526A · kind A · utility
18Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.