Memory insensitive to disturbances
US5570313A · kind A · utility
19Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1995 |
| Grant date | Oct 29, 1996 |
| Priority date | — |
| Expiry date | Oct 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a memory cell insensitive to disturbances. The memory cell, that contains information in the form of two complementary logical levels (X, C(X)), each logical level being stored in a node of the cell (N1, N2), is characterized in that it comprises means of storing the same logical level in two different nodes (N1, N2, N3, N4), the said means being able to restore any logical level to its initial state preceding a modification made on it due to a disturbance, as a result of holding the value of one of the two logical levels complementary to the logical level that was modified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.