Dual bank memory system with output multiplexing and methods using the same
US5570320A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 1995 |
| Grant date | Oct 29, 1996 |
| Priority date | — |
| Expiry date | Nov 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit 300 is provided which includes first and second banks 201a and 201b of memory cells arranged in rows and columns. Row decoder circuitry 210 is provided for selecting a row in at least one of the banks in response to row address. Row address circuitry 208, 209 is included for providing a sequence of row addresses to the row decoder circuitry in response to a single row address received at an address port to memory circuitry 300. Column decoder circuitry 213 is provided for selecting columns in each of the banks 201 in response to a column address. Column address circuitry 211, 212 is provided for presenting a sequence of column addresses to the column decoder circuitry in response to a single column address received at the address port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.