Synchronous DRAM tester
US5570381A · kind A · utility
14Cited by
4References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Oct 29, 1996 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.