Apparatus and method of making laminate an embedded conductive layer
US5571608A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1995 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | Sep 5, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/31765
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An embedded core laminate including a conductive reference plane interposed between two insulation layers, and further interposed between two conductive layers. The assembly is laminated using standard temperature and pressure laminating procedures. Holes for interconnect vias are preferably drilled into the reference plane before laminating. The resulting embedded core laminate has three conductive layers with relatively uniform separation, insuring improved impedance control on each PCB (printed circuit board). Since uniform separation is maintained from one PCB to another, multiple PCBs connected together using embedded core laminates according to the present invention allows minimum cross-talk and characteristic impedance variations from one PCB to the next. The material comprising the conductive layers are preferably chosen with a CTE to match that of semiconductor die to protect solder joints of mounted components from thermal stress, improving reliability of SMT devices and allowing direct chip attach methods to be implemented. Balanced PCBs having five, seven and other odd numbers of conductive layers are available using an embedded core laminate material according to the p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.