Antifuse with silicon spacers
US5572062A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1994 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | Mar 31, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and resulting antifuse structure in an integrated circuit include a first metal interconnection layer on a first insulating layer over the substrate of the integrated circuit, a second insulating layer over the first metal interconnection layer. The second insulating layer has a via therein and a programming layer is located in the via. Such programming layer includes a first region on the first metal interconnection layer which is removed from sides of the second insulating layer in the via, and a second region on the sides of the second insulating layer via. The first region has substantially a first thickness, the second region has substantially a second thickness which is greater than the first thickness. Upon programming the antifuse structure, a conducting link forms in the first region of the programming layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.