Power supply configured sensing scheme for flash EEPROM
US5572465A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 1995 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | May 25, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bias selector circuitry for a memory cell sensing circuit is described. The bias selector circuitry includes a reference voltage generator, an output node, and a selector. The output node provides the bias voltage to the reference bitline load and the sense bitline load for controlling the reference and sense bitline node voltages, respectively. The selector provides a first bias voltage to the output node if a power supply voltage is at a first level. The selector selects the reference voltage generator to provide a second bias voltage to the output node if the power supply voltage is at a second level. The reference bitline node voltage is maintained at approximately the midpoint of the operating range of the sense bitline node voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.