Address comparison in an inteagrated circuit memory having shared read global data lines
US5572467A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1995 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | Apr 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.