Transparent memory mapping mechanism for a digital signal processing system
US5572695A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1994 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | May 31, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.