Cache access controller and method for permitting caching of information in selected cache lines
US5572700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache access controller and method for controlling access to a cache memory are implemented in a computer system having a processor for performing memory access operations specifying an address in main memory, and a cache memory comprised of a number of cache lines. The cache access controller includes a control circuit which produces a number of access values in response to the address, each access value being associated with a cache line and having a true or a false state. The controller also includes an access logic circuit which permits the caching of information associated with the address at a cache line if the access value associated with that cache line is true. An operator register and a parameter register associated with a cache line may be used in conjunction with the address to determine the access value for that cache line using arithmetic, logical, or a combination of arithmetic and logical, functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.