Bus snoop method and apparatus for computer system having CPU with cache and main memory unit
US5572701A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 19, 1994 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | Apr 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.