Apparatus and method for immediately stopping clocks
US5574393A · kind A · utility
3Cited by
8References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1992 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Dec 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/13
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.