Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling
US5574872A · kind A · utility
22Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1994 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Jun 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and method implemented in a processor, having a pipeline and trap generation capabilities, for indicating a pipelined instruction and for generating a trap upon modification of the pipeline. Improved trap handling capabilities and improved overall system performance is provided by reducing unnecessary saving and restoring of the pipeline during certain trap handling procedures, such as those that do not modify the state of the pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.